
module top();
	
	reg clk;
	reg[7:0] data;
	reg[7:0] out_data;

	initial begin
		clk = 0;
		data = 0;
	end

	always #50 clk = ~clk;

	always @(posedge clk) begin
		data <= data + 1;
		$display("data: %d, out_data: %d\n", data, out_data);
		if (data > 254) begin
			$finish;
		end
	end

	delay delay(.clk(clk), .rx(data), .tx(out_data));
endmodule
